1. Field of the Invention
The present invention relates to a local silicon-oxide-nitride-oxide-silicon (SONOS)-type nonvolatile memory device and a method of manufacturing the same. More particularly, the present invention relates to a local SONOS-type nonvolatile memory device in which an oxide-nitride-oxide (ONO) layer and a control gate are formed in a self-aligned manner, and a method of manufacturing the same.
2. Description of the Related Art
A nonvolatile memory device can electrically erase and store data and retain data even if power supply is interrupted. The nonvolatile memory device has increasingly been applied in various fields such as mobile communication systems and memory cards. In recent years, a nonvolatile memory device having floating-gate-type cells has been widely used. However, as the integration density of semiconductor devices increases, it becomes more difficult to scale down and pattern cells. For this reason, a nonvolatile memory device having SONOS cells (hereinafter, a SONOS-type nonvolatile memory device) was proposed as a substitute for the floating-gate-type nonvolatile memory device. The SONOS-type memory device can be integrally formed with peripheral regions and/or logic regions of an integrated circuit (IC), and the manufacture thereof is relatively simple.
FIG. 1 is a cross-sectional view of a conventional SONOS-type memory device.
Referring to FIG. 1, an ONO layer 20 is formed on a silicon substrate 10 where source and drain regions 30a and 30b are formed. The ONO layer 20 comprises a tunnel oxide layer 12, a nitride layer 14, and an upper oxide layer 16, which are sequentially formed on the silicon substrate 10. A control gate 25 is formed on the ONO layer 20. This SONOS-type memory device is referred to as a stack SONOS-type memory device.
The nitride layer 14 is a memory (storage) layer that controls the threshold voltage (Vth) of a cell and stores data by trapping electric charges in a trap site or emitting the electric charges from the trap site. The upper oxide layer 16 is a blocking layer that prevents the loss of electric charges.
The driving operation of the stack SONOS-type memory cell is as follows. Initially, if a predetermined positive voltage is applied to each of the control gate 25 and the drain region 30b, and the source region 30a is grounded, electrons are injected from an inversion region formed between the source and drain regions 30a and 30b into the tunnel oxide layer 12, and the nitride layer 14 traps the electrons that have passed through the tunnel oxide layer 12. In this operation, data is written or programmed in the memory cell. In FIG. 1, reference character A denotes a trapped electron region. If the control gate 25 is charged with negative charge and a predetermined voltage is applied to the source region 30a, holes in the silicon substrate 10 pass through the tunnel oxide layer 12 and are trapped in the nitride layer 14, and then the trapped holes are recombined with the electrons that have been trapped in the nitride layer 14. In this operation, the written data is erased from the memory cell.
In this stack SONOS-type memory device, although electric charges are stored in a portion (the region A of FIG. 1) of the nitride layer 14, the ONO layer 20 is entirely interposed between the control gate 25 and the silicon substrate 10. Thus, the stack SONOS-type memory device has a high initial threshold voltage and a high program current. Because of the high threshold voltage, power dissipation is high and it is difficult to integrally form the stack SONOS-type cell along with a typical logic device having a low initial threshold voltage in a single chip. Also, since the electrons that are trapped in the nitride layer 14 may move along the nitride layer 14 in a horizontal direction, the erase operation of the SONOS-type memory device may be incomplete. As the program operation and the erase operation are alternately performed, the initial threshold voltage may increase, thus reducing a data retention time.
To solve the above-described problems, a local SONOS-type memory device, in which a charge trapping layer, i.e., a nitride layer, partially overlaps a control gate, was proposed. A conventional local SONOS-type memory device and a method of manufacturing the same will be described with reference to FIGS. 2A through 2C.
Referring to FIG. 2A, a tunnel oxide layer 52, a nitride layer 54, and an upper oxide layer 56 are sequentially stacked on a silicon substrate 50. Next, a first photoresist pattern 58 is formed, and the upper oxide layer 56, the nitride layer 54, and the tunnel oxide layer 52 are patterned using the first photoresist pattern 58.
Referring to FIG. 2B, the first photoresist pattern 58 is removed, and a gate oxide layer 60 is formed on the silicon substrate 50. Thus, while a portion of the silicon substrate 50 is covered by the gate oxide layer 60, the other portion thereof is covered by an ONO layer 62. Thereafter, a conductive layer for a control gate, for example, a polysilicon layer 65, is deposited on the gate oxide layer 60 and the ONO layer 62. A second photoresist pattern 66 is formed on the polysilicon layer 65 to define the length of a control gate.
Referring to FIG. 2C, the polysilicon layer 65 and the ONO layer 62 are patterned using the second photoresist pattern 66, thereby defining the lengths of the control gate 65a and the ONO layer 62. The second photoresist pattern 66 is removed. Here, the control gate 65a overlaps the gate oxide layer 60 and the ONO layer 62. Impurities are doped into the silicon substrate 50, thereby forming source and drain regions 68a and 68b. 
In this local SONOS-type cell, the ONO layer 62 partially overlaps the control gate 65a. Thus, the initial threshold voltage and erasing time can be reduced. However, in the local SONOS-type cell, the length of the control gate 65a and the length L of the ONO layer 62 are defined by a photolithography process, which may lead to a loading effect and a misalignment.
For example, the second photoresist pattern 66 for defining the control gate 65a may be misaligned during the photolithography process as shown in FIG. 2B, thus changing the length of the ONO layer 62. That is, if the polysilicon layer 65 and the ONO layer 62 are patterned using the misaligned second photoresist pattern 66′ of FIG. 2B, the length of the ONO layer 62 (or the overlap length L1 or L2 of the ONO layer 62 with the control gate 65a) vary for each memory cell.
The operating characteristics, for example, erasing speed, erasing efficiency, and initial threshold voltage, of the local SONOS-type cell depend on the overlap length L of the ONO layer 62 with the control gate 65a, which is almost the same as the length of the nitride layer 54. Accordingly, it is required to minimize a variation in the overlap length L of the ONO layer 62 with the control gate 65a. 
For example, when the second photoresist pattern 66 is aligned as shown in FIG. 2C, L is 150 nm. However, when the second photoresist pattern 66′ is seriously misaligned as shown in FIG. 3, L1 is about 200 nm and L2 is about 100 nm. This variation in the overlap length causes a variation in the threshold voltage of the local SONOS-type cell. Also, since a patterning process is performed using a photolithography process, the scaling down of a memory device is limited due to the exposure limit of a photolithography apparatus.